Integrated circuit memories have become increasingly dense as the need for more memory storage increases. While fabrication techniques and design options have been fairly successful in maintaining steady increases in memory storage from design generation to generation, the need for new highly populated circuits continues.
A dynamic random access memory (DRAM) device is typically comprised of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted internally on signal lines, referred to as bit or digit lines, which are coupled to input/output lines through transistors used as switching devices.
Sensing circuitry is included in the memories to both sense data stored in the memory cells and amplify the data for outputting. The sensing circuitry typically compares a charge stored on a memory cell with a known reference. The physical space required to implement both the communication lines and the reference circuits limit the density possible on a given integrated circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a dynamic memory circuit which maximized the available space of a memory array, including the edges of the array.